verilog based Real Time clock with manual input implement on fpga

用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program

此程序为串行通信程序,采用verilog语言编写的,经过仿真验证已经通过.-This procedure for the serial communication procedures, the use of Verilog language, after simulation has been adopted.

基于FPGA的JPEG图像压压缩，实现JPEG图像的实时压缩 (Real-time compression pressure compressed FPGA-based JPEG images, JPEG images)

关于硬件描述语言Verilog的135个经典实例，从易到难，对Verilog的编程有很大的帮助。(About the Verilog hardware description language 135 classic example, from easy to difficult, for Verilog programming of great help.)

用vhdl编写的主从式代码，会比较接近，它涉及i2c接口，主从式，每行都有注释，我建议如果你想对代码进行编辑就使用灵活的编辑器

使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)

前导零的计算 (Calculation of leading zeros)

基于EDA技术的数字密码锁源程序代码,大学实训用的着-EDA-based Digital code lock source code, used by the University Training

一个数码管的驱动开发程序，程序完备，可以直接使用，在开发板上使用时注意改变引脚(A digital control of the driver development program, the program is complete, can be used directly, when used in the development of attention to change the pin board)

包括VHDL、verilog在内的各种设计实例，是学习硬件描述语言的帮手。共有82个实验例子，涉及各种语法规则。-82 VHDL, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper.