verilog based Real Time clock with manual input implement on fpga

台湾IC中心VHDL讲义，内容详细，适合IC前端设计参考(Taiwan s IC Center VHDL handouts, detailed reference design for front-end IC)

由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)

基于芯片MAX502的十二位并行DAC芯片的程序，利用FPGA中的ROM查表进行数据存储-Based on 12 of the MAX502 chip DAC chips in parallel procedures, the use of FPGA in the ROM look-up table for data storage

fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz

VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.

VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)

IIC控制器 for Sopc Builder-IIC controller for Sopc Builder

数字电子钟设计完整设计，包括原理介绍，程序设计，波形仿真-Design a complete digital electronic clock design, including the principle of introduction, program design, waveform simulation

VHDL参考例程--日如DAC0832接口电路程序-VHDL reference routines- on procedures such as the DAC0832 Interface Circuit

cvery high compatibles for quartus