实用的程序代码，希望对大家有用，已经调试通过

USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents

verilog 驱动TLC5510代码，TLC5510是高速的AD，可达20MHz(verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz)

其中两个项目自己做的：一个是雷达模拟跟踪，基于FPGA/CPLD的，里面包含了PCB和VHDL码，还有一个是SDIO的驱动程序（包括PCB原理图，SDIO协议方面的资料还有就是源码，这项目可用），还有一些嵌入式方面的资料，如TCP/IP协议栈的实现，FPGA的一些仿真实例(Two of the projects themselves to do: a tracking radar simulator is based on FPGA/CPLD)

按键可调占空比的PWM波产生程序。语言：VHDL(Button adjustable duty cycle of the PWM wave generator. Language: VHDL)

该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)

hdmi 视频编解码输入输出模块，verilog实现(hdmi encoder and decoder in verilog.)

该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)

内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM

fpga平台实现srio通信，以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.