USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including...

说明：  本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.)

SDIO Verilog Sourcw code

基于EDA技术设计4位十进制数字频率计的系统方案-Based on EDA technology design four decimal system solutions Cymometer

it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates

PIC单片机学习软件及其资料，入门到精通(PIC MCU learning software and its information, entry to proficiency)

vhdl对dds的原理设计，由衷要得论文价值。不后悔-right dds VHDL design principle, we sincerely value of fine papers. No regrets

FPGA驱动adc9226，高精度高速度。(ad9226 by FPGA)

此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16(this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY)

this is a sum for 2 digit numbers

429总线通过FPGA直接实现发送程序,通过Verilog实现(send 429 message by Verilog and FPGA )