USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including...

该计数器可以实现从0到1000的技术，程序简练执行效率高(counter1000)

40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )

加法计数器的VHDL工程，程序，仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU

    本资源详细的设计了一个FIFO的用法，将数据从ROM中读取送到FIFO缓存中然后RAM从FIFO缓存中读取数据存到内存中，改程序可以很好的学习三者之间的关系

protel中fpga封装库2，非常难找的-protel library 2 in fpga package, very difficult to find the

8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn

MX25L6445E开发时间，Verilog语言(MX25L6445E development time, Verilog language)

基于EPM1270的PS2键盘鼠标驱动源码Verilog-Based on the EPM1270 the PS2 keyboard and mouse-driven Verilog source

具有桥式结构的传感器很多，如利用应变原理、磁电阻原理和其他变电阻原理的传感器，可以实现对压力、位移、加速度、磁场等物理量的测试。这种结构的差分输出可以增加灵敏度，也有一定抵消外加干扰的能力。而且有的虽不是差分输出，比如电阻分压式的输出，可以认为是“半桥”，我们还可以人为的加上另一半，即加上一对精密电阻和一个电位器组成另一个分压电路，形成差分输出。每次调节电位器使差分输出为0，抵消零磁电压。-Bridge structure with many sensors, such as the use of contingency theory, the principle of magneto-resistance and other variable resistance sensor principle can be achieved on the pressure, displacement, acceleration, magnetic field, such as physical tests. The structure of the differential output can increase sensitivity, but also have some ability to offset the additional interference. And some is not a differential output, such as pressure resistance of the output type, you can think is

在Qaurtus环境下用Verilog输入实现64QAM信号的发生，用MATLAB协助验证，观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)