FPGA的存储器代码的VHDL,verilog描述及测试代码

SDIO 接口，实现SD卡的控制器功能，带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)

DEMO中完成WIAGAND26/32的（EMP7128实现）协议程序源代码-DEMO completed WIAGAND26/32 (EMP achieved) agreement procedure source code

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

vga接口的工程实现，基于altera环境，需要的可以-vga interface engineering implementation, based on altera environment, need to take a look at

CPU 5级流水线实现（加hazard处理与板级验证，板级验证带有按键消抖）(5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce))

fsk在matlab上的仿真实现，一段简单的代码小程序(fsk on matlab simulation in the implementation of a simple small program code)

WCDMA数字直放站中数字预失真研究及其FPGA实现(WCDMA Digital Repeater digital pre-distortion and its FPGA implementation)

de2-115引脚的配置，quartusII的设置(de2-115 configuration pins, quartusII settings)

vhdl八位十进制数字频率计的设计，顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)

说明：  Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)