used in the preparation of Verilog FLEX10K achieve simple CPU

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

verilog 或门程序 初学者必备。。。。。。。。。。。。(verilog )

PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF

Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave

VHTL PROGRAMMING COURSE

本文是自已写的电子密码锁的详细开发过程，用的是Modelsim进行仿真实现，打开文档lzp-This article is written in their own electronic locks detailed development process, using a ModelSim simulation achieved, open the document lzp

Wimax矩阵的LDPC编码器，已通过modelsim仿真测试，并前在altera的FPGA板上通过测试,码率5/6，可进入代码内部修改参数，支持2/3,3/4其他2个码率，数据吞吐量为700M(Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m)

system gen & accel dsp 培训资料-system gen & accel dsp

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

This source is used to control 7 segments on FPGA boad