关于VHDL编程的教程,比较系统的讲解,很有用的书

FFT程序，此程序虽然耗逻辑资源很大，但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据，对要求时延较低的系统可以考虑-FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower

4 级流水方式的8 位全加器。。。。。。(Way flow of 4 full adder 8. . . . . .)

电子琴程序设计与仿真的vhdl实现的源代码-Electronic organ program design implementation and simulation of vhdl source code

用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0

Matlab agc ʵ

全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code

这里面有很多的vhdl的编程的源代码，文件是全英文的，例子丰富(That there are a lot of vhdl programming source code, documentation is in English, and examples of rich)

RFID防碰撞算法的研究，以及对其各种算法的仿真，以及改进算法的仿真和比较。(RFID anti-collision algorithm, as well as its simulation algorithms, and improved simulation and comparison algorithms.)

Verilog经典教程，非常好的资料！值得一看！(Classic Verilog tutorials, very good information! Worth a visit!)

一个小寄存器堆，使用参数化编程，附有仿真代码，可直接在vivado（2018.2版本及以后）上运行(A small register heap, using parametric programming)