全数字锁相环的verilog源代码

当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter

布尔乘法器带testbench好用的工程啊(Boolean multiplier works with testbench nice ah)

可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.

说明：  基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。(FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.)

状态机的性能考察.rar 状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar

半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

在MATLAB的SIMULINK中，用DSPBUILDER实现计数功能，控制LED指示灯.(In MATLAB SIMULINK, DSPBUILDER is used to realize counting function and control LED indicator lamp.)

Leonardo综合器用STDL80 0.5um综合库，安装见说明，找到它真不容易。(STDL80 0.5um ASIC Library for Leonardo)

基于SDRAM的PCI采集,上位机为VC编写，桥芯片为PLX9054，项目已经做完，上传5个例程，已经验证通过(SDRAM, PCI-based acquisition, PC for VC preparation, bridge chip for PLX9054, the project has been done, upload 5 routines, has been verified by)

This programa execute calc of CRC by use a table.