verilog full case and paralel case directive usage

用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)

这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)

NIOSII I2C接口模块及驱动程序，并含有测试程序。对想开发NIOS的工程师很有帮助(NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful)

half band filter code

1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core manual 7.2 5.verilog to achieve serial transmission)

Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.

基于uc3842的反激电路的saber仿真模型，可调制，波形结果完美(The saber of the flyback circuit simulation model based on uc3842, modulation, waveform perfect results)

DW8051单片机的设计，用HDL设计，详细的HDL设计-DW8051 microcontroller design, HDL design, detailed design of the HDL

ddr3使用教学(DDR3 using teaching)

实现输入一正弦波和噪声的叠加，介绍详细欢迎下载(The input of a superposition of sine wave and noise introduced in detail)