VHDL_Led control single light from right to left( điều khiển led sáng dồn từ phải sang trái)

HDB3 ENCODING AND DECODING METHOD

EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功(EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success)

NIOS II IDE 编程， uart_txd测试程序，仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.

cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures

利用stm32F407实现的等精度测频，可以精确测量频率，误差很小(The equal precision frequency measurement realized by stm32F407 can accurately measure frequency with little error.)

本文提出了一种新颖的可逆乘法器。可逆逻辑可以发挥重要作用

VHDL基本运算，采用8位为乘法器，将两个8位字符串的值输入相乘后

This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.

hash加速器的verilog实现，也用于fpga或asic(hash verilog rtl )

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)