FPGA to design in ECU, very help for engineer

用于FPGA实现单总线测温电阻DS18b20时序。在xilinx spartan 3中试过。-failed to translate

用硬件描述语言编程实现减法器,实现两个操作数的减法-Using hardware description language programming subtraction, and the achievement of the two operands of the subtraction

des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language

mux one hwich is teh best knwo progerma i n the workdl and ist is the

NCO 代码设计 使用VHDL语言 (nco)

Computer Arithmetic (press 2000)

使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)

一个vhdl实现的hamming码编码器-an hamming coder using vhdl

ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)

说明：  4位加法器，4位数字相加及进位功能的实现，主要利用Verilog语言实现，简单轻松，且代码量少(a adder which can realize 4 bit numbers adding)