Verilog HDL编写的总线功能模型，十分有用，需要的下载

用vhdl做的计算机组成原理课程设计的资料，实现加法运算，进行求和，仿真实例等资料！-Vhdl to do with the computer information on the composition of curriculum design principles to achieve the addition operation, a sum, simulation examples, etc.!

本程序设计一个基于FPGA的4相步进电机定位控制系统。由步进电机方向设定电路模块、步进电机步进移动与定位控制模块和编码输出模块构成。前两个模块完成电机旋转方向设定，激磁方式设定和定位角度的换算等工作，后一个模块用于对换算后的角度量编码输出。-This procedure to design an FPGA-based 4-phase stepper motor positioning control system. Direction set by the stepper motor circuit module, stepper motor stepper movement and positioning control module and the code output modules. The first two modules complete the motor rotation direction setting, exciting way of setting the angle and positioning of the conversion work, after a module for the point of view of the volume of converted output encoding.

7对于进入密码锁的按键，假设复位后七个灯显示" 0"，而使用sw5、sw6 2，则只要按下并松开sw5后七个灯就显示" 5"，而只要按下并松开sw6，七个灯就正确显示值" 6

4-16译码器，用VHDL编写的，可以直接下载到可编程逻辑器件中(4-16 decoder, written with VHDL, can be directly downloaded to the programmable logic device)

USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language

bch编解码的完整版，本人已经做过fpga实现，就是按照该程序为原型，绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)

在Quartus环境下编写，使用Cyclong系列芯片，配置七通道高精度AD5791，该例子为AD5791的FPGA配置使能代码,包括模拟数据输入模块，复位模块，命令接收是能配置模块。(AD5781，Digital signal convert to Analog signal)

Once the FPGA is located, the rest of the mapping data for the other components can be determined dynamically its section mapping registers.

DDR SDRAM控制器verilog代码及中文说明文档(DDR SDRAM Controller Using Virtex-5 FPGA Devices)

说明：  使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)