Verilog HDL编写的总线功能模型，十分有用，需要的下载

说明：  basic verilog code on siso, piso, sipo

Coding Styles for if Statements and case Statements

获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)

通信系统的FSK调制程序，比较实用，包括完整的工程-FSK modulation communication system procedures, more practical, including the complete works

在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器-Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory

FM接收机 基于FPGA的调频收音机的设计 用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真(FM receiver on FPGA FM receiver design With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation)

原创：cos函数和sin函数的VHDL实现，很实用(cos of the VHDL implementation)

mult,在quartusII中，以模块输入形式，仿真乘法器mult，得到时序图和功能图(a simulation example of mult)

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

SDRAM控制器 带仿真模型文件 仿真通过(Simulation model file simulation through SDRAM controller)