通用存储器VHDL代码库,The Free IP Project VHDL Free

Xilinx公司网站下的SDRAM Controller的参考设计，经过验证-Xilinx website of SDRAM Controller reference design, validated

40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )

本例程使用vivado2014.4工具，利用xilinx Basys3 实验板实现板载流水灯的两种模式控制。(This project uses verilog HDL to realize the the control of 16 leds loaded on Xilinx Basys3 board.)

基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)

利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的-Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the

vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control output (square A duty cycle is also controllable), can store data of arbitrary waveform characteristics and able to reproduce the waveform, but also through a variety of linear superposition of the waveform output.

veirlog编写的PS2键盘通讯程序, 并有PS2接口的相关说明, Quartus II 8.1工程文件(veirlog written communication procedures PS2 keyboard, and a PS2 interface instructions, Quartus II 8.1 project file)

modelsim快速入门教程，附带文中范例源代码。-ModelSim Quick Start Guide, incidental text in an example of source code.

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)

用 vhdl 语言实现，上下计数器使用边缘触发一个 4 位纹波计数器。积极的边沿触发。 包含的所有文件。试验台架波形。针对采用赛灵思文件