通用存储器VHDL代码库,The Free IP Project VHDL Free

三相PWM整流，实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ，can maintain the stable DC voltage)

xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)

用VHDL语言实现TDMA编码,简单，明了。看标注就可以看懂-use vhdl langhanTDMA

利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图，回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)

xillinx Spartan6 FPGA DDR 接口设计指南(xillinx Spartan6 FPGA DDR Interface Design Guidelines)

实现按键控制AD三通道的电源转换的功能。(AD three buttons control channel to achieve power conversion)

VHDL_count 从 0000 到 9999 7 段 LED 显示器 （đếm 慈 0000 đến 9999 hiển 施耐 4 领导 7 đoạn）

Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license

应用背景****************************************************************************关键技术这个项目的目的是研究开发板的最大。该项目是实现闪烁的发光二极管具有不同的频率和/关闭时，你按按钮。

LDPC的编码模块和解码模块，实现802-3an协议的编码(The module of LDPC to implement the coding of the 802-3an protocol)