4 位纹波计数器

the basic system of nexys3(soft core)

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

moltiplicatore floating point

verilog 语言实例，对于新手学习有很大帮助的实例-Examples of Verilog language, the novice has to learn very helpful examples of

基于状态机的优秀SPI输出程序（以DAC7512为基础，可修改）(VHDL code about SPI)

An FPGA Implementation of a HoG-based Object Detection Processor

Altera大学计划程序包，基于Nios II的源代码-Altera University program package, based on the Nios II source code

verilog RTL code for simple TCAM

利用两个加法器和两个乘法器一起并行处理来实现

说明：  资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。(According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.)