4 位纹波计数器

JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.

Xilinx FPGA make 50 smaller-Xilinx FPGA make 50 smaller

六十进制计数器用于计数等操作，代码的实现方式很简单(Six decimal counter for counting operation, the code is very simple implementations)

这是基于MIMO-OFDM的对CFO进行估计的源程序，对分析此同步算法有着非常重要的作用。(This is based on the source of the MIMO-OFDM of the CFO estimation, on the analysis of this synchronization algorithm has a very important role.)

自己编写的C++的类的测试程序，有详细的注注释，对初学者有很大帮助！！！(The own written C++ class test program, detailed annotation of Note of great help for beginners! ! !)

Ethernet MAC-MII interface of Transmit

SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解)(SPI in Verilog implementation (a very comprehensive and detailed, but also with the SPI algorithm annotation))

是用于pci开发的核，可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间 (Pci developed for nuclear, hardware information can be mapped to the inter-ran up to save the developers time to understand the hardware)

《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6

quartus ii 环境下，一个完整的利用TEXTIO仿真的源代码，包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)