4 位纹波计数器

flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench

本源码详细介绍了UART的经典实例，敬请下载，谢谢适用-The source described in detail a classic example of UART, please download, Thank you apply

Syplify经典英文教程。内含众多实验例程，Lab 1 Basic Synplify Run；Lab 2 Analyzing Critical Path and Assigning Timing；Lab 3 FSM (Finite State Machine) Compiler Constraints and Attributes(Syplify classic English tutorial. Contains numerous experiments routine, you can help learners to quickly grasp Syplify tips, is a rare foreign experiments tutorial.)

FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)

Xilinx的I2C总线控制器，verilog版本，文档号是XAPP333，可到Xilinx网上查找具体说明，有对应的VHDL版本的-Xilinx

这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.

说明：  基于FPGA，用verilog hdl语言实现串口收发实验(Based on FPGA, using Verilog HDL language to achieve serial port transceiver experiment)

用Actel公司的Fusion系列FPGA开发的LCD实验程序-Fusion with Actel s FPGA development series LCD Experimental procedures

WOLA polyphase filter加权跌接累加FFT信道化技术(WOLA polyphase filter bank)

基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)