4 位纹波计数器

说明：  FPGA与PC端实现串口数据的收发，先从PC端接收数据，然后发回给电脑，可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)

Clifford E. Cummings论文合集，其中关于FIFO的设计很经典(Clifford E. Cummings collection of papers, on the FIFO design classic)

ldpc编码器ru算法的verilog语言的完整实现，希望对您有用(ldpc encoder, RU, VERILOG，altera)

8选1程序，是利用vhdl编写的，自己弄得还能用，上传下(8 Select a program is written using vhdl, allowed herself can use to upload the next)

说明：  Xilinx vivado 权威教程，清华大学出版社出版，何宾编著。(Xilinx vivado authoritative course, published by Tsinghua University Press, edited by He Bin.)

在FPGA内使用PID算法反馈控制小车速度和方向，四电机独立(PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors)

class diagram diagram for AIRS

verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)

VHDL Code For Full Adder By Data Flow Modelling

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been