DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M...

说明：  本书从电子技术和通信系统的角度讲解gps接收机的设计开发原理，其内容集中在用户终端，即接收机的设计原理和软件实现上。全书分为两大部分，第一部分为理论篇，第二部分为实现篇。理论篇首先对导航的基本目的进行了阐述，并由一个浅显的二维导航系统对导航信号的特点进行了推导，随后阐述了gps信号格式，同时对于直接影响接收机性能的射频前端部分做了理论分析；实现篇主要对本书实现的软件gps接收机的系统实现和源代码进行了讲解，同时作为总结，将信号处理的结果和有意义的中间变量以图示的方式给出，可以使读者有一个感性的认识，同时提升学习兴趣。. 本书适合从事卫星导航接收机研发的技术人员和卫星通信接收机研究的研究人员，尤其是从事北斗系统研发的专业人员、cdma通信系统研发人员，以及通信电子类专业的高年级本科生和研究生阅读，既可作为教学培训的教材，也可作为相关专业工程技术人员的参考资料。(This book explains the design and development principle of the GPS receiver from the perspective of electronic technology and communication system. Its content focuses on the design principle and software implementation of the user terminal, that is, the receiver. The whole book is divided into two parts. The first part is the theoretical part and the second part is the realization part. Firstly, the basic purpose of navigation is expounded, and the characteristics of navigation signal are deduced by a simple two-dimensional navigation system. Then, the format of GPS signal is expounded. At the same time, the front-end part of radio frequency which directly affects the performance of the receiver is theoretically analyzed.)

说明：  半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

FPGA设计频率计全套资料，我希望对大家啊好似有用的-FPGA design of a full set of frequency data, I hope all of you ah like useful

FPGA控制外边led，并实现跑马灯等多种效果，用户可以自行控制(FPGA control outside led)

JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis

protel经典教程，并附有一张电路设计原理图(protel classic tutorials, together with a circuit design schematic)

一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench

vhdl的源文件调试 ！！！！！！！！ flv视频-VHDL source file debugging! ! ! ! ! ! ! ! flv video

spi接口的eeprom模型，型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)