DSP 程序的测试 很有用的 仪器上面用的

此代码是SPI接口的Master的Verilog源代码，经上板测试是没有问题的，请大家放心使用 (This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use)

verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^

ps2 vga interface in vhdl code

verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)

说明：  实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

vhdl的3-8译码器-instantiate the 3-8 decoder

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

基于NIOS驱动ALTERA DE1开发板的GPS模块工程-based on the nios ii drive the gpa module of altera de1 develop board,it s only a reference project

本例为DAC0832接口电路VHDL原代码-The DAC0832 Interface Circuit Example for VHDL source code

2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列，伪随机序列，曼彻斯特编码 程序 和单片机部分程序(2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program)