DSP 程序的测试 很有用的 仪器上面用的

VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.

基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

hdmi 视频编解码输入输出模块，verilog实现(hdmi encoder and decoder in verilog.)

电子设计自动化中关于交通信号的转换的实现程序，基于VHDL语言实现的-Electronic design automation in the conversion of traffic signals on the realization of the procedure, based on the realization of VHDL language

说明：  misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!

说明：  利用正点院子开拓者fpga实现DDS功能，实现三角波、正弦波、方波的发生。(Implementation of DDS with FPGA)

Interface for ADS8361 TI ADC IP Core for ALTERA NIOS2

使用FPGA控制永磁同步电机的代码，实现对永磁同步电机的控制功能。(Motor control by using FPGA)