DSP 程序的测试 很有用的 仪器上面用的

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典-Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!

采用STC89C52单片机的定时器以实现两路PWM波输出，占空比、频率可调(Microcontroller timer used to achieve STC89C52 two PWM wave output, duty cycle, frequency adjustable)

用Verilog语言实现汉明编码，很粗燥，是大三的时候做的(With the Verilog language Hamming code, it is rough dry, a junior at the time to do)

65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程-65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole algorithm analysis including input a sum then multiply in the process

基于可编程逻辑器件实现任意波形发生器VHDL源代码-Programmable logic device based on the arbitrary waveform generator implementation VHDL source code

this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code

关于vhdl对硬件接口8237的编程，可以在进行fpga/cpld设计是作为模块用到-VHDL for the hardware interface on the 8237 programming, you can carrying out fpga/cpld design is used as a module

艾米电子的液晶1602的Verilog语言程序 (Amy e-LCD 1602 of the Verilog language program)

FPGA开发,DE2开发板上实现,从SD卡读出MP3文件并播放,(即是开发一个简单的MP3播放器)(FPGA development, DE2 development board realize, from the SD card to read out and play MP3 files, (that is, the development of a simple MP3 player))

设计一个模块，从一个窜行数据流里检测出码流“11100”，这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch