Synchronous Resets Asynchronous Resets I am so confused! How will I ever know wh...

VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners

配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

应用背景当你按下一个按钮有一个反弹的效果，因为金属零件连接另一个按钮是不理想的，导致一个读错误的微控制器。如果我们有一个按钮，打开或关闭一个LED，如果我们不实施反弹跳过滤器（软件或硬件）将不准确的击键。有时apretará和LED不行动。关键技术软件解决方案是基于实现代码过滤按键最少x毫秒是不稳定的，所以我们知道什么是对的和别人接触是不考虑

一个很有用的vhdl实用教程，很适合初学者学习，介绍了vhdl的一些基本概念，还有一些经典的实例。-A useful practical VHDL Tutorial, it is suitable for beginners to learn, introduced some basic concepts of VHDL, there are some classic examples.

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.

对锁相环路的仿真，二阶环的仿真与分析都可以通过这个文件来到完成(Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came)

有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层次的仿真。 -The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment usi

自己写的 AXI master code(AXI master code)

利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)

verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."