Synchronous Resets Asynchronous Resets I am so confused! How will I ever know wh...

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the

James Armstrong VHDL Design , source code

利用AT89C51实现LCD日历电子钟源码-AT89C51 realization of the use of electronic LCD calendar clock source

VHDL实现的超前进位加法器-the VHDL-ahead Adder

matlab dsp building 工程欢迎下载(matlab dsp building )

cadence verilog lanaguage and simulation course

LMS算法自适应滤波器的Matlab仿真分析.(LMS matlab fangzhenchengxu.)

MaxplusII编写的简易cpu，可实现简单加减法等操作(MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc)

调制解调器是在发送端通过调制将数字信号转换成模拟信号，而在接收端通过解调将模拟信号转换为数字信号的一种装置。这个程序用VHDL语言编写，实现了二进制振幅键控（2ASK）的调制与解调；二进制频移键控（2FSK）的调制与解调，二进制相位键控（2PSK）的调制与解调过程。

msk比特误码率matlab仿真 匹配滤波器(the msk bit error rate matlab simulation matched filter)