基本的 VHDL 程序

16X2液晶显示屏的FPGA显示驱动设计。-16x2 LCD display driver design of the FPGA.

System Generator

基于altera系列芯片lvds接口的fpga设计 verilog源码-Series altera-based chip interface lvds source fpga design verilog

verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel

频率计，vhdl语言， ispDesignEXPERT-Frequency meter, vhdl language, ispDesignEXPERT

串口！ 这是一个使用的通信程序 ， 非常好用。(serial port Serial port! This is a communication program used, very useful.)

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,

去抖动状态机,外部按键转换状态,同时可去抖动-To shake state machine, the external key conversion state, while to the jitter

verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。(verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.)

detection of the following sequence ‘10110110’in VHDL