数字时钟的VHDL语言描述，具有高精度，控制性能良好

verilog实现的串口实现代码，可以直接复制使用(verilog achieve serial implementation code can be copied directly use)

DSP28335与FPGA通过spi通信，此程序为28335为主接收程序(DSP28335 and FPGA through the SPI communication, this procedure for the 28335 receiving procedures)

说明：  处理器系统，处理器加上存储器，从存储器取出指令放入处理器执行(processor system, instructions stored in ROM, a counter generate address and the processor execute instructions.)

说明：  QUARTUS2 16.9 VHDL FPGA ENDAT2.2

xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN module.

一些vhdl的简单例子。直接解压，不用密码。-instantiate some simple examples. Direct unpack, without a password.

HDB3编码器与解码器，以及RTL图，使用Verilog HDL实现(HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement)

vhdl实现的鼠标协议，代码可读性高，适合作为参考案例。-VHDL realize mouse agreement, the code readable, suitable as a reference case.

用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0

将FPGA设计仿真结果数据写入到txt记事本中，然后通过Matlab读取txt中的数据并显示图像(write the FPGA simulation result data into textbook,and read these data from textbook and display image in Matlab)