电子闹钟：基于fpga的电子闹钟设计，采用模块化方式

设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count 和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电 平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一 个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))

The project is used to perform the operation of 4 bit arethmatic and logical operation. the projcet is implemented in spartan 3E

一个可综合的同步FIFO的verilog源代码-An integrated synchronous FIFO in Verilog source code

costas载波恢复算法 锁相环路，注释很清楚(costas carrier recovery algorithm PLL)

ALTERA on chip fifo. this document is from altera. good resouce

try this for pq improvmnett

16QAM调制解调程序画出时域波形、 正交分量、同相分量波形，眼图，散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)

Service Manual LG TV LCD DISPLAY models 2011

说明：  多路信号复用基带系统的建模与设计,按位同步复接并掌握四路同步复接器的VHDL设计及系统的时序仿真。(library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all )

DDS实验 matlab 与quartus 的完美结合(DDS experimental combination of matlab and quartus)