基于ALtera公司的若干款FPGA的调试经验，对初学者有重要价值

UART模块的VHDL语言设计(Design of VHDL language based on UART module)

SPI读写AD9361，通过串口回读关键寄存器读写是否正确。(SPI reads and writes AD9361, reads and writes the key registers correctly through the serial port.)

基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。

说明：  Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.

通过上翻键和下翻键来设置方波信号正负脉冲宽度，利用一排流水灯来显示按键的次数，通过观察流水灯亮的盏数确定占空比（按一次上翻键亮一盏灯，流水灯全亮时占空比调到了最高或者是最低状态，按一次下翻键灭一盏灯，流水灯全灭时占空比调到了最低或者是最高状态）。(Duty cycle of LED lights and adjustable oscilloscope display code)

8051单片机VHDL内核,内有说明,很详细,值得下载-8051 VHDL core, which has made it clear that, in great detail, it is worth downloading

CPLD对mcbsp的收发操作，占用资源很少(CPLD to mcbsp transceiver operation, small footprint)

用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

介绍如何使用vivado来调用和封装IP核，测试AXI4总线的三种功能协议。(It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.)