交通灯的ＶＥＲＩＬＯＧ实现，含详细中文注释．

In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them includes all the VHDL source codes of the component.)

source code for Ethernet logic

基于FPGA的视频图像加密系统 DE2_70+TRDB—D5M+VGA(FPGA-based video encryption system DE2_70+TRDB-D5M+VGA)

PI控制器的算法及源码，迅速掌握FPGA的VHDL算法实现！(Algorithm and source code of PI controller, quickly grasp the implementation of VHDL algorithm in FPGA!)

实现基于FPGA的控制MCP2515发送的程序，本人编写通过测试，希望提供帮助(FPGA-based control program sent MCP2515, I write to pass the test, hoping to help)

说明：  基于BP算法的LDPC译码程序，采用vhdl语言，bp算法(BP algorithm based on LDPC decoding program using vhdl language, bp algorithm)

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)

An Alarm Project Writen in VHDL for FPGA Devices

ethernet 10 0M MAC-ethernet MAC 10,100 M

2008-2009年优秀硕士论文之：基于FPGA的高性能32位浮点FFT IP核的开发(Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development)