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SOPC_PCI
基于FPGA的pci总线接口设计。。。。。。。。。。。。。(FPGA-based PCI bus interface design)
- 2012-03-28 13:55:33下载
- 积分:1
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GUI
1)选择一个语音信号作为分析对象,或录制一段语音信号; 2)对语音信号进行采样,画出采样前后语音信号的时域波形和频谱图; 3)利用MATLAB中的随机函数产生噪声加入到语音信号中,使语音信号被污染,然后进行频谱分析; 4)设计用于处理该语音信号的数字滤波器,给出滤波器的性能指标,画出滤波器的频率响应; 5)对被噪声污染的语音信号进行滤波,画出滤波前后信号的时域波形和频谱,并对滤波前后的信号进行比较和分析; 6)回放各步骤的语音信号,给出相应处理程序及运行结果分析。(1) Select a voice signal as an analysis object, or record a voice signal 2) sampling the voice signal, draw the waveform and frequency spectrum of the time domain before and after sampling the speech signal 3) using the random function in MATLAB generated noise was added to the speech signal, the speech signal to be contaminated, and then spectrum analysis 4) for processing the speech signal, the digital filter design, given the performance of the filter to draw the filter' s frequency response 5) on the noise pollution of the speech signal is filtered, time-domain waveform and spectrum draw before and after filtering the signal before and after filtering, and the signal for comparison and analysis 6) playback of the speech signal for each step, given the results of the corresponding processing procedures and run analysis.)
- 2021-03-18 17:29:19下载
- 积分:1
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DDS_signal_genarator
这是一个利用verilog语言编写的信号发生器的例子,值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)
- 2013-12-23 10:12:52下载
- 积分:1
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divf_even
基于FPGA cyclone2的偶数分频模块,可实现自定义分频数(Based on FPGA cyclone2
even number of frequency divider module, custom frequency divider can be realized.)
- 2018-11-06 12:11:46下载
- 积分:1
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To increase simulation speed, ModelSim® can apply a variety of optimizations...
To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
- 2022-03-06 09:05:21下载
- 积分:1
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Verilog HDL系列和转换的准备。我用电流输出类型。股份有限公司...
Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
- 2022-06-18 11:27:00下载
- 积分:1
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xiawenyu-verilog-
数字系统设计的入门书,教你如何学会用verilog语言实现各种数字逻辑功能,例程经典易懂(xiawenyu verilog)
- 2012-02-18 11:40:39下载
- 积分:1
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51SCMTutorial
《精彩51单片机教程》适合初学者,很难得(" Discover the 51 SCM Guide" for beginners, very rare)
- 2010-09-10 20:26:39下载
- 积分:1
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pngenerator
pngenerator的vhdl代码。我们可以在cdma的fpga实现中使用它;
- 2022-10-01 04:45:03下载
- 积分:1
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edc_spi_command
单片机和FPGA的通信程序,发送5个数,传输稳定,可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)
- 2013-09-14 21:09:52下载
- 积分:1