数码管时钟

Pipeline processor verilog components

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

FPGA based design and Implementation of Advanced Encryption Standard

wimax ofdm系统评估代码 wimax ofdm system code 很有参考价值(wimax ofdm system code)

适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT

这是用verilog语言实现的1024点ff程序t-This is achieved using Verilog 1024 language ff procedures point t

直接序列扩频通信的Verilog仿真代码，在Quartus II中实现。(Direct sequence spread spectrum communication Verilog simulation code, implemented in Quartus II.)

一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)

说明：  关于quartus与modelsim 仿真(about quartus and modelsim simulator)

出租车自动计费系统，功能完善，方便快捷，十分好用-taxi