cpld 控制 8

说明：  document qpsk vhdl code

FPGA Verilog控制FLASH片外读写(Verilog Controls FLASH Out-of-Chip Read-Write)

编程规范是重中之重，带你书写良好的变成习惯(It is used to measure noise and detect road noise pollution. It is accurate and has good effect.)

Verilog语言描述，统计图片的像素值直方图(Verilog，Pictures of the pixel value histogram statistics)

CPLD下载线制作，内含电路图等，希望对大家有帮助-CPLD download line production, including circuit diagrams, etc., in the hope that we have to help

程序来自《现代通信系统－使用matlab》英文版 已经调通！并加上了注释。 希望对大家有帮助4(fpga)

自动化仿真平台的搭建使用代码，经过具体的仿真和优化，发现代码完全可用(The automated simulation platform is built using code, and after specific simulation and optimization, it is found that the code is fully available)

根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从而发出音乐声，实验表明，采用该方法设计的音乐发生器成本低、修改方便-Music took place in accordance with the mechanism of complex programmable logic device, as occurred in the core of music devices, with high-speed integrated circuit hardware description language to describe the occurrence of music notation, with the peripheral hardware circuits, electro-acoustic conversion by the audible signal device to receive signals, which issued music, experiments show that this method of music generator design and low cost, easy to amend

有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)

使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过(Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by)