-
展位乘数 VHDL 源代码
8位有符号编码的整数基改性
- 2022-06-14 01:22:33下载
- 积分:1
-
ComChange-12061629
说明: 并行读写14路串口数据,数据被写入FIFO,在收到读写信号后,SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)
- 2019-03-13 01:38:44下载
- 积分:1
-
adder
This the adder VHDL code, it contains input and output fild, also simulate file-adder
- 2022-06-21 18:48:32下载
- 积分:1
-
lcd1602_drive
用Verilog实现1602的配置及功能。正确编译与实现(Realized by Verilog 1602 configurations and functions. Compilation and implementation of the right)
- 2011-01-21 16:47:27下载
- 积分:1
-
DESHTM
用VHDL语言实现了DES加密算法,其中包含了测试程序,能够进行仿真。(Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.)
- 2009-03-15 12:29:56下载
- 积分:1
-
Altera QUARTUS 7.2的矩阵键盘电子琴完整工程(含源码),在EP2C20芯片上实现...
Altera QUARTUS 7.2的矩阵键盘电子琴完整工程(含源码),在EP2C20芯片上实现-Altera QUARTUS 7.2 Project of matrix keyboard electronic organ, implement on EP2C20 chip.
- 2022-02-01 23:23:04下载
- 积分:1
-
本书是一本Verilog语言设计和综合手册,对学习Verilog语言有很大作用,值得阅读....
本书是一本Verilog语言设计和综合手册,对学习Verilog语言有很大作用,值得阅读.
- 2023-03-07 07:25:03下载
- 积分:1
-
FPGA_UART
说明: FPGA串口实现。
发送和接受数据功能代码(FPGA serial interface. Send and receive data function code)
- 2010-05-04 00:15:23下载
- 积分:1
-
ug_dsp_builder
本文是Altera公司编写的dspbuilder的设计方法,但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)
- 2008-12-14 01:33:58下载
- 积分:1
-
cnt60
de2开发板上的一个小程序 模60的计数器/分频器(de2 board developed a small program module 60 of the counter/divider)
- 2011-11-28 20:28:12下载
- 积分:1