protel library 2 in fpga package, very difficult to find the

实现beep发出1234567的音乐声音-beep 123456

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第二个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The second document

vhdl对dds的原理设计，由衷要得论文价值。不后悔-right dds VHDL design principle, we sincerely value of fine papers. No regrets

说明：  Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)

本程序是fpga控制flash的读写程序，包括了程序和仿真时的测试文件(fpga flash)

quartus ii 环境下，一个完整的利用TEXTIO仿真的源代码，包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)

vedic multiplication

verilog编写的ds18b20温度传感器程序，可综合(ds18b20 program written in verilog)

SPI经典ip核 可以直接用于工程的开发和利用-err

SDIO slave verilog code