VHDL basic arithmetic library, a very handy! !

本实验教程选用Xilinx公司的产品X9572，与之配套的开发软件为ISE4.1i，可进行原理图的输入和VHDL硬件描述语言的输入，并且可利用Modelsim进行功能仿真和时序仿真。-In this study, selected Xilinx tutorial products X9572, with supporting the development of software for ISE4.1i, schematic can be input and VHDL hardware description language input, and can use Modelsim functional simulation and timing simulation.

联邦滤波法，毕设时写的，可以和其他方法的做比较(Kalman filter, write the complete set up, and other methods to compare)

Synopsys 8051 IP core documentation.

实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)

这个程序是为了区分SIGNAL和VARIABLE在不同情况下要怎样使用的例程，程序中使用了三种情况来说明问题(This program is designed to differentiate between routine SIGNAL VARIABLE in different situations and how you want to use, the program uses the three cases to illustrate the problem )

This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.

FPGA 帧同步源代码 调试无错误 ALTERA 平台(Frame synchronization FPGA)

内容太短。注意请： 代码没有很好的描述将被删除，你不会得到任何点。请描述一下更好地获得更多积分。

《FPGA数字信号处理与工程应用实践附光盘》配套源代码(FPGA DSP and their applications with verilog HDL)

attachement of attachments..bits pilani