本例为ADC0809接口电路VHDL程序原代码

利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter

数字频率计毕业论文 不是自己做的-Digital Cymometer thesis do not own. . Ha ha

内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用(Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly)

8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.

一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS )

说明：  i2c module，有i2c主机和从机模块(i2c module verilog VHDL base on i2c protocol)

VHDL的四选一选择器-VHDL four elected a selector

vga编程。实现3种模式的vga控制，分别产生横彩条，竖彩条，棋格彩条的显示-vga programming. Realization of the three-mode vga control, generate horizontal color of the color of the shaft, and the chess grid color of the show

该工程用verilog编写，已通过串口调试助手调试通过，接收模块采采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。 (The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC spontaneous self-closing function.)

自己写的扩展功能时钟，增加了年、月日计时，verilog代码，已在spatarn3实现。-Write their own extensions clock, an increase of the year, month day time, verilog code in spatarn3 realize.