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RS485
verilog开发FPGA,实现RS485串口通信(RS485 driver for FPGA )
- 2021-02-08 06:49:54下载
- 积分:1
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xiaomi
新版 小米抢购器 -源码
已经测试,代码很有用,已经抢了好几个小米3了,希望对大家有用(The new millet to snap up- source
Have test, the code is useful, has robbed several millet 3, hope useful for everyone)
- 2014-01-08 18:26:40下载
- 积分:1
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xilinx-FPGA
xilinx FPGA技术详解,从设计流程到设计注意点(xilinx FPGA technology Detailed Design points, from the design process to)
- 2012-08-10 13:07:41下载
- 积分:1
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pcf8563
pcf8563,在quartusII下VERILOG编写的数字时钟程序,8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)
- 2013-12-24 21:46:21下载
- 积分:1
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用VHDL编写的8259控制,供大家使用.
用VHDL编写的8259控制,供大家使用.-with VHDL control of the preparation of the 8259, for your use.
- 2023-07-08 01:55:02下载
- 积分:1
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在 VHDL 中的离散余弦 Transform(DCT/IDCT)
项目目的是设计 DCT 和 IDCT 在 VHDL 中。离散余弦变换图像压缩中用于压缩的 JPEG 图像。此文件包含 DCT 和 IDCT 块和顶级模块于一体的两个块和矢量来测试这两个模块。
- 2022-02-05 11:13:18下载
- 积分:1
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ADC
AD转换的Matlab程序,将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率),然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)
- 2012-12-18 11:01:40下载
- 积分:1
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at96
isa总线接口,可以实现与isa总线 的IO和MEMERY接口(isa bus interface can be achieved with the isa bus IO interfaces and MEMERY)
- 2008-05-15 20:36:51下载
- 积分:1
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一个用VHDL完成的8位数显的16进制的频率计
一个用VHDL完成的8位数显的16进制的频率计-a VHDL completed 8 of 16 significant median band of frequency meter
- 2022-01-31 16:47:07下载
- 积分:1
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AD_R
AD7685芯片采集程序,可以自行设置采样率,经检验可用。(The AD7685 chip collection procedures, available.)
- 2020-12-20 14:19:08下载
- 积分:1