verilog HDL编写的出租车计费系统

verilog开发FPGA，实现RS485串口通信(RS485 driver for FPGA )

新版 小米抢购器 -源码 已经测试，代码很有用，已经抢了好几个小米3了，希望对大家有用(The new millet to snap up- source Have test, the code is useful, has robbed several millet 3, hope useful for everyone)

xilinx FPGA技术详解,从设计流程到设计注意点(xilinx FPGA technology Detailed Design points, from the design process to)

pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)

用VHDL编写的8259控制,供大家使用.-with VHDL control of the preparation of the 8259, for your use.

项目目的是设计 DCT 和 IDCT 在 VHDL 中。离散余弦变换图像压缩中用于压缩的 JPEG 图像。此文件包含 DCT 和 IDCT 块和顶级模块于一体的两个块和矢量来测试这两个模块。

AD转换的Matlab程序，将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率)，然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)

isa总线接口，可以实现与isa总线　的IO和MEMERY接口(isa bus interface can be achieved with the isa bus IO interfaces and MEMERY)

一个用VHDL完成的8位数显的16进制的频率计-a VHDL completed 8 of 16 significant median band of frequency meter

AD7685芯片采集程序，可以自行设置采样率，经检验可用。(The AD7685 chip collection procedures, available.)