verilog HDL编写的出租车计费系统

使用LPM_ROM的实际的例子-Use of practical examples LPM_ROM

vhdl的一个串行序列信号发生器的设计与实现-vhdl sequence of a Serial Signal Generator Design and Implementation

un controller pi par le langage VHDL xilinx ise design 13.2

介绍VHDL编程的资料，很详细，值得收藏-vhdl

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

verilog实现的“六进制约翰逊计数器”。(verilog implementation of the " six hexadecimal Johnson counters." )

try this for pq improvmnett

FFT算法的VHDL语言实现 可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging

_EDA实验讲义EDA实验指导书EDA技术与VHDL第3章EDA技术实用教程EAD技术与实践.等等资料-Experimental _EDA experimental guidance notes EDA books EDA technology and VHDL in Chapter 3 of EDA technologies utility EAD Technology and Practice Guide. And so on Information

五级流水线CPU实现（带Hazard），还没来得及实现Cache求高人指教(pipeline CPU with Hazard)