FPGA实现打车计程系统

循环冗余校验码(试验报告)-Cyclic Redundancy Check (pilot reports)

结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source

基于FPGA的门级逻辑实现快速乘法运算的verilog源程序。-FPGA-based gate-level logic implementation of rapid multiplication of the verilog source.

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

24,60,100进制的计数器，还有数字时钟，欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~

使用CPLD进行驱动电机演示，使用硬件编程语言，适合初学者-use of motor-driven CPLD for a demonstration of the use of hardware programming language, suitable for beginners

Crossroad traffic lights with visualization in tcl/tk and verilog code

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

序列检测VHDL源代码，ATERA平台编译。详细的报表说明和模拟源代码。

利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！-Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware description language of the people to see!