硬件描述语言

说明：  从github下载的，能够参考设计AXI4的协议接口(AXI4 Verilog template)

基于EDA的八音自动播放电子琴设计 内有VHDL语言设计 有-The octave-based EDA player automatically have a flower design language VHDL design

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

四位除法器的VHDL源程序-four division of VHDL source

4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率.-4-channel 12-bit AD chip AD7862 control module, VHDL source code, suitable for single conversion sampling, 250K sampling rate.

HDL example source code 3/5 jkff_a

Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave

this example finds the gapes that are existed in a word

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

FPGA读SRAM中的数再传给CY7C68013-Reading SRAM in the FPGA, then pass on a few CY7C68013