FPGA源代码

说明：  bnn-fpga是FPGA上CIFAR-10的二进制神经网络（BNN）加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC，并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时，错误率是11.19％。(bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%.)

ip核的FFTverilog源代码，说明不是很具体-ip nuclear FFTverilog source code, that is not very specific

说明：  一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)

用verilog实现的一个2抽头RLS自适应滤波器的代码(A realization with verilog HDL code of a two-tap RLS adaprive fliter )

采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件-AD using high-speed storage oscilloscope design, based on EP1C3 board GWADDA board storage oscilloscope, which has the documentation

uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps

HDLC协议的FPGA实现，运用了VHDL语言，主要就是解封帧HDCL，平切添加了外部接口

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件-Such as precision digital frequency of a project- including VHDL source code and compile the relevant documents after

关于i2c master/slaver control 方面的技术资料 介绍其特色与使用方法(On the i2c master/slaver control of technical information on their characteristics and use)

AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)