登录
首页 » VHDL » usb控制器,有VHDL实现的,还有C++的源码,可以编译

usb控制器,有VHDL实现的,还有C++的源码,可以编译

于 2022-03-31 发布 文件大小:104.61 kB
0 145
下载积分: 2 下载次数: 1

代码说明:

usb控制器,有VHDL实现的,还有C++的源码,可以编译-usb controller, there is the realization of VHDL, as well as C++ source code can be compiled

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • mul24x24
    24位x24位的乘法器 十分详细24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器(24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplication Explorer 24-bit x24 multiplier 24-bit x24-bit multiplier)
    2009-06-08 10:00:58下载
    积分:1
  • LDPC.DIFFERENT-CODE-LONGTH
    LDPC码不同码长对比。码率选择1/2.码长分别为256,512,1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)
    2012-11-22 10:53:04下载
    积分:1
  • jt2
    基于FPGA的交通灯代码,VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)
    2013-10-26 13:30:26下载
    积分:1
  • Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法...
    Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms
    2023-06-15 23:20:03下载
    积分:1
  • DE2_115_NIOS_DEVICE_LED
    DE2-115开发板LED显示测试源码,对fpga开发者提供参考(DE2-115 development board LED display test source, provide a reference for fpga developer)
    2011-09-29 15:07:10下载
    积分:1
  • str
    these are verilg prgms
    2012-12-05 18:12:51下载
    积分:1
  • shukongfenpinqi
    数控分频器的设计 数控分频器的功能就是当在输入端给定不同输入数据时,将对输入的时钟信号有不同的分频比,例3的数控分频器就是用计数值可并行预置的加法计数器设计完成的,方法是将计数溢出位与预置数加载输入信号相接即可。(NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different frequency than, for example 3 is to use the NC prescaler count preset value of the adder parallel counter design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.)
    2008-12-13 09:56:51下载
    积分:1
  • FPGA设计全流程-软件综合使用、
    FPGA设计全流程-软件综合使用、 -FPGA design of the whole process- the integrated use of software, FPGA design of the whole process- the integrated use of software,
    2022-12-25 07:35:03下载
    积分:1
  • Altium_Package_LMH0340
    Altium Reference design for LMH0340 test bed and design
    2013-05-11 04:21:35下载
    积分:1
  • c51
    51数字钟带各种扩展年,月,日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)
    2012-11-09 08:41:02下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载