usb控制器，有VHDL实现的，还有C++的源码，可以编译

LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)

2位并行加法器初学者必看初步了解FPGA-two count

半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)

一个简单的FM调制模块，FM发射，用Verilog编写，基于Xilinx SPARTAN6 XC6LX9开发(A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development)

64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核(64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS)

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

fpga的一个小程序用于3s500e 4*4键盘模块(fpga is a small program used 3s500e 4* 4 keyboard module)

AHB master总线verilog实现(Implementation of AHB master bus Verilog)

设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能。(Design of a decimal counter, a display position with the count clock in at around eight digital scrolling function.)