cy68013 vhdl code and usb high speed

本程序是锁相环的仿真程序，具有接收端载波同步的功能。注释详尽，程序规范。发端的调制方式有单载波调制，BPSK调制，QPSK调制可供选择。程序中有星座图，锁相环的频差、相差图，以及解调后的基带波形。(This program is a phase-locked loop simulation program, the with carrier synchronization receiving end function. Notes detailed program specifications. The originator of the modulation scheme to choose a single carrier modulation, BPSK modulation, QPSK modulation. Program constellation diagram, the PLL frequency difference, a difference of FIG, and the demodulated baseband waveform.)

ADI ad9361 vivado 下源代码(ADI ad9361 vivado source code)

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

基于sopc的7352的ad模块的nios软核多通道编写,verilog 写的(The sopc 7352 AD module nios soft core multichannel write. Rar )

常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题-Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging

通过VERILOG编写的AD9516时钟芯片SPI配置代码(CONGIGURE THE ad9516)

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第四个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The fourth document

说明：  实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)

一个可综合的同步FIFO的verilog源代码-An integrated synchronous FIFO in Verilog source code

本项目接收高清 sdi 广播的视频，并将其转换为 HDMI 接口的显示器上显示。 这个项目只需要 20 位的视频数据和从它和使用标志首先 YCbCr 视频数据转换为 RGB 数据，然后编码到 HDMI 提取时间标志。 本模块需要 74.25 MHz 的时钟。