一个可综合的同步FIFO的verilog源代码

基于FPGA的等精度数字频率计，包含FPGA和单片机通信程序，解释非常详细。经过调试成功。(FPGA-based Precision Digital frequency meter, including FPGA and MCU communication program, explained in great detail. After successful commissioning.)

我用的是二进制分频的方法，这种分频方法的分频只能是2n次方，有限制，但是很方便

说明：  单周期cpu，使用verilog编写的的单周期cpu支持......等功能(Single cycle CPU, using Verilog written single cycle CPU support... And other functions)

在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意-QuartusII warning solving

I2C接口标准建模源码,I2C interface standard modeling source-I2C interface standard modeling source

串口程序 VHDL-Serial procedures VHDL

基于FPGA用verilog语言实现16点FFT(16-point FFT FPGA-based verilog language)

该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)

cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program

一个模拟ISA界面的简易小程式，简单易懂-ISA interface, a simple simulation of a small program, easy-to-read