一个可综合的同步FIFO的verilog源代码

 交通灯控制器控制红（r）、绿（g）、黄（y）三种不同颜色的交通灯，这三种不同颜色灯的亮、灭分别由三个定时器（timer1、timer2、timer3）控制；  当某个定时器工作时，它所控制的交通灯亮，直到设定的定时时间到（该定时器状态由’0’变’1’），交通灯跳转到另一种状态；  clk是脉冲控制端（图中未标出）；reset是异步复位端，复位状态为红色交通灯亮；  输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。 ( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control  When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state  clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights  output terminal r, g, y represent the three colors of traffic lights bright, the off state.)

FPGA的驱动并行接口的DAC程序，效率较高。(FPGA-driven parallel interface of the DAC process more efficient.)

多年项目经验测试文档测试文档，重要保存重要保存重要保存重要保存重要保存重要保存(Years of project experience testing document testing, it is important to save save save important important important important to save save save important)

一个视频信号输入的verilog源代码，里面含有相关的使用文档。-A video signal input of the Verilog source code, which contains documents related to the use.

Xilinx fpga 设计培训中文教程,比较好的学习FPGA入门的教程(Xilinx fpga design training for Chinese curricula, better start learning FPGA Tutorial)

用VERILOG语言实现的通用异步串行收发器（RS232收发器），波特率可设置，通讯稳定，已成功应用于实际项目。(VERILOG language with universal asynchronous serial transceivers (RS232 transceiver), the baud rate can be set, communication stability, has been successfully applied in actual projects.)

It s Flicker_LED code.Verilog for MaxV.

非常好的SDRAM Controller 设计文档。工程必备-SDRAM Controller Design of a very good document. Works required

简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)

EDA应用中RAM具体定义实例，供大家学习和写程序参考之用-EDA applications, examples of the specific definition of RAM, for everyone to learn and write programs for reference