一个简单的总线bus代码，初学者可以借鉴学习

基于FPGA的PCM编码器与解码器的设计-about fpga and pcm

VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code

in this code very useful for designing real number concept

xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation

实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)

VHDL硬件描述语言与数字逻辑电路设计-VHDL hardware description language and digital logic circuit design

16位并行乘法器源代码，booth2编码，二进制树拓扑结构(16bits parallel multiplier source code )

DDS在现在运用月来越广泛，在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平，为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continuity, quadrature output, high-resolution and integration, and other aspects far more than the traditional frequency synthesizer technology can achieve the level To provide a superior analog signal source performance. DDS technology can be used very easily to a variety of signal. FPGA Implementation of DDS

基于FPGA与LM4550B的AC97软声卡VHDL语言驱动，版本2.0-FPGA-based soft and LM4550B the AC97 sound card driver VHDL language, version 2.0

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )