使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供 初学者参考...

基于FPGA的多功能电子时钟的设计很经典的哦-FPGA-based multi-functional electronic clock designs are very classic Oh

endat 2.2 接口内核，发送命令至编码器或从编码器接收位置值(endat 2.2 interface cores, sending commands to the encoder or received the encoder position values)

用VHDL语言写的，音乐演奏程序，范例歌曲为“青花瓷”片段。-Using VHDL language, and music performance procedures, examples of songs as

LCD12864的显示程序，使用的是verilog语言编写的显示程序，为PDF文档(LCD12864 display program, using Verilog language display program, as a PDF document)

 交通灯控制器控制红（r）、绿（g）、黄（y）三种不同颜色的交通灯，这三种不同颜色灯的亮、灭分别由三个定时器（timer1、timer2、timer3）控制；  当某个定时器工作时，它所控制的交通灯亮，直到设定的定时时间到（该定时器状态由’0’变’1’），交通灯跳转到另一种状态；  clk是脉冲控制端（图中未标出）；reset是异步复位端，复位状态为红色交通灯亮；  输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。 ( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control  When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state  clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights  output terminal r, g, y represent the three colors of traffic lights bright, the off state.)

32位扰码器的verilog代码，编译通过(The Verilog code of 32_bit scrambler)

RS码的FPGA实现，verilog语言形式，好参考资料(FPGA realization of RS code, verilog language form, a good reference)

Project manager is reak vhdl old man

matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

运用VC编程的带LCD显示的信号发生器可用三个开个调节输出三个波形(Signal generator can be used three to open a regulator output waveform using VC programming with LCD display)