Divider can be very good VHDL divider realize the function of great help for beg...

altera 的reed solomn 设计(reed solomn design from altera)

vivado入门使用介绍，初学者入门学习(vivado Instructional pdf)

基于FPGA的Verilog语言的智能小车，已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)

说明：  这是一款由晶振产生的脉冲控制的数字钟，可以从00:00:00到23:59:59之间进行计时。(this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.)

there are exemple in the vhdl

《Verilog HDL 程序设计教程》5-"Verilog HDL Design Guide" 5

（1）能够测试10HZ~10MHZ的方波信号； （2）电路输入的基准时钟为1HZ，要求测量值以8421BCD码形式输出； （3）系统有复位键； （4）采用分层次分模块的方法，用Verilog HDL进行设计，并对各个模块写出测试代码； （5）具体参照说明文档（包含源代码，仿真图，测试波形，详细的设计说明）(A square wave signal capable of testing 10HZ~10MHZ; (2) the reference clock input by the circuit is 1HZ, and the measured value is output in the form of 8421BCD code; (3) the system has a reset key; (4) adopt the method of layering sub sub module and design with Verilog HDL; (5) write test simulation program.)

vhdl编的dds函数发生器，完成sin(x)曲线的生成-vhdl function generator dds compiled to complete the sin (x) curve is generated

说明：  FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.