利用两个半加器来组成的全加器，是简单的vhdl语言入门

嵌入式的LCD的图片显示程序，是LCD最好的资料。(Embedded LCD picture display program is the best LCD data.)

FPGA讲义适合中等以上读者，主要是FPGA的一些高级应用-FPGA notes for readers more than moderate, mainly a number of advanced applications FPGA

GMSK vhdl generated from simulink

USB+FPGA电路设计原理图，实际的电路板运行正常，很有参考意义。-usb_sch

采用Verilog HDL设计，在Altera EP1S10S780C6开发板上实现 选取6MHz为基准频率，演奏的是梁祝乐曲 - Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music

vc707 board ucf xdc files

一个verilog语言开发编写的简单的ddr3模型(A simple model ddr3, written with verilog language)

FPGA代码，Designing_with_Quartus_II_Exercises_Ver11_v4_2.doc-FPGA code Designing_with_Quartus_II_Exercises_Ver1 1_v4_2.doc

说明：  一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)

用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication