利用两个半加器来组成的全加器，是简单的vhdl语言入门

DE2将连接到LCD布局上，为Terasic off技术公司附上系统代码

adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz

基于FPGA的超声波测距，通过数码管显示距离(FPGA-based ultrasonic distance)

说明：  vcs中文使用教程，帮助你快速入门Linux下的VCS操作(VCs Chinese tutorial to help you get started with VCs operation under Linux)

program for half subtractor.

用verilog hdl编写的一些例程，包括加法器/减法器等等，例子较多就不一一列举了(Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the)

huawei代码编码规范，包含基本的verilog的语法等编码规范，业界经典(Huawei code coding specification, including the basic syntax of the Verilog code, the industry classic)

电子设计自动化中关于交通信号的转换的实现程序，基于VHDL语言实现的-Electronic design automation in the conversion of traffic signals on the realization of the procedure, based on the realization of VHDL language

蛋蛋助手,可以动态配置生成代码格式,方便ORM或或程序员的生成工作 ，经测试 (Egg assistant, can be dynamically configured to generate code format, convenient ORM, or programmer generation work, tested)

说明：  通过SPI接口实现FPGA和MCP2515独立CAN芯片通信，功能使用modelsim仿真，实现了配置、接收、发送功能。(The communication between FPGA and MCP2515 independent can chip is realized by SPI interface. The function is simulated by Modelsim, and the function of configuration, receiving and sending is realized.)