利用两个半加器来组成的全加器，是简单的vhdl语言入门

该工程用verilog编写，已通过串口调试助手调试通过，接收模块采采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。 (The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC spontaneous self-closing function.)

安富利SP605开发板ISE12.4版本的XBD文件，里面包括了开发板所有的接口，包括硬件和软件设计(Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design)

可编程器件厂商Altera出品的8b10b编码器源代码(Giga8b10b v10)

说明：  基于FPGA的液晶显示控制器的设计，FPGA用的是EP2C5,LCD用的是ST7920内核的122*32点阵的LCD，显示中西文字符(FPGA-based LCD display controller design, FPGA is used EP2C5, LCD is used in the ST7920 core of 122* 32 dot matrix LCD, display of Chinese and Western characters)

encoder using else if statement

一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS )

VHDL实现快速傅里叶变换，内附带资料以及源代码。(VHDL fast Fourier transform, within the supplied data and source code.)

说明：  Ovo sto saljem je tutorijal 7 sa vhdlom

MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构-ModelSim simulation developed CPU, using VHDL language description of the structure of the use of cumulative