数码管显示有片选 模块 四输入，与其他模块相连即可使用

信号完整的一些总结，非常实用，适合开始着使用(A book for signal integrated)

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

xilinx 的8B10B编解码源码, 里面有仿真模型,用以测试验证(xilinx 8B10B encode/decode source)

说明：  SDRAM控制，通过VHDL语言编写可运行至133MHz。(SDRAM control, written in VHDL language, can run to 133MHz.)

基于VHDL语言描述的一个分频器，根据端口值，可作为四分频，八分频等分频器使用。-based on VHDL description of a divider, according to port value, as a quarter of frequency, Frequency Divider interval such use.

红外接收处理，根据外部波形记录波形的高低电平时间，从而得到波形数据。(Infrared receiver processing, according to the external waveform waveform record high and low times, resulting waveform data.)

verilog ADPLL file with testbench

CPLD对mcbsp的收发操作，占用资源很少(CPLD to mcbsp transceiver operation, small footprint)

说明：  uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

this come from alter ,you can look and find it on line.