Wishbone dma ip core

FPGA UART 发送端程序 verilog语言编写 9600波特率 实用(UART transmit side program verilog language 9600 baud)

基于CPLD的签到器的设计，用三维数组队人名进行储存-Based on the attendance CPLD design, a few team names with three-dimensional storage

SystemVerilog For Design (Springer-2nd_Ed-2006)

基于QUATEUS2的设计一个8位频率计verilog语言编程(The design is based QUATEUS2 an 8-bit frequency counter verilog programming language)

double edfe trigger d latch

离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.

A program for a simple multiplexer using modelsimSE6.3

VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

说明：  SDRAM控制，通过VHDL语言编写可运行至133MHz。(SDRAM control, written in VHDL language, can run to 133MHz.)