Wishbone dma ip core

基于 verilog的卷积运算代码，应用于离散小波分析。(verilog conv)

我感谢我能找到这个页面WAP相同的帮助。我在开始设计的VHDL的电路。

采用Verilog HDL设计，在Altera EP1S10S780C6开发板上实现 选取6MHz为基准频率，演奏的是梁祝乐曲 - Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music

本例介绍直接合成带阻滤波器的方法，n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop coupled resonator elliptic filters is presented. Two different coupling schemes, which both include source–load coupling are used. The first coupling and routing scheme is the standard folded structure used in implementing bandpass elliptic filters with transmission zeros using resonators.)

fpga永磁同步电机矢量控制系统，包括死区等模块(fpga foc)

800 x 480 / inch lcd

  基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码 use IEEE.std_logic_unsigned.all; package outconverter is constant stage : natural := 3; constant FFTDELAY:integer:=13+2*STAGE; constant FACTORDELAY:integer:=6; constant OUTDELAY:integer:=9; function counter2addr( counter : std_logic_vector; mask1:std_logic_vector; mask2:std_logic_vector ) return std_logic_vector; function outcounter2addr(counter : std_logic_vector) return std_logic_vector; end outconverter; package body outconverter is function counter2addr( counter : std_logic_vector; mask1:std_logic_vector; mask2:std_logic_vector ) return std_logic_vector is variable result :std_logic_vector(counter"range); begin for n in mask1"range loop if mask1(n)="1" then result( 2*n+1 downto 2*n ):=counter( 1 downto 0 ); elsif mask2(n)="1" and n/=STAGE-1

电子密码锁的vhdl编程实现，不知以前有没有人做过的。-electronic locks VHDL programming, I wonder if the past is not done.

lap of altera . it s basic about verilog

flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench