开发环境：maxplus2 a/d convortor

VGA显示控制：时序控制+像素点的颜色处理显示十字光标（vorilog）(VGA Display Control: Timing Control+ pixel color processing and display cross cursor (vorilog))

signaltap 中文说明，内容详细。 ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)

接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated data The compressed package includes the Verilog code, the testbench code Matlab simulation code)

实现I2C协议下EEPROM存储的数据读写控制(Under I2C protocol to achieve read and write data stored in EEPROM control)

基于FPGA的调制，实现了QPSK调制，所用芯片为Artera的CycloneIIEp2C5T114C8-FPGA-based modulation, realize the QPSK modulation, the chip used for Artera

ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的Kay法(QPSK-carrier frequence offset estimation_ kay )

它是一个8051 VHDL源代码发布的原创。

DDS分频实现，全部代码的完整过程，包括截图等(DDS divider to achieve the complete process of all the code)

说明：  FPGA实现Jpeg压缩，和视频采集程序(Zynq - Main - register access Mio)