开发环境：maxplus2 a/d convortor

动态获取CPU使用率源码 可以加到压力测试里(Dynamic access to CPU use the source code )

d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )

说明：  基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。 FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board. FPGA edge detection)

pex8311代码实现 altera的fpga 代码编程 实现本地读写 pex8311_test

vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control output (square A duty cycle is also controllable), can store data of arbitrary waveform characteristics and able to reproduce the waveform, but also through a variety of linear superposition of the waveform output.

说明：  misp，五级流水源码，实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)

matlab仿真MATLAB电机仿真精华50例--源代码异步电机\asymotor_stator.mdl

说明：  QPSK的解调程序，采用Verilog编写而成(QPSK demodulation program, written by Verilog)

USB245I的基于FPGA的VHDL语言的驱动程序,应该有用-USB245I based FPGA VHDL of the driver, should useful

扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation