浮点乘法Verilog FPGA

LDPC encoder and decoder, very simple

硬件描述语言相关芯片程序源码Chip hardware description language-related program source code(Chip hardware description language-related program source Chip hardware description language-related program source code)

When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.

数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法(Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods)

说明：  lvds_rx IP核硬件设计代码，使用时注意LVSD_RX模块的延时参数的设置，3.5倍时钟相位的设置(Lvds IP core hardware design code, when using the attention LVSD module delay parameter settings, 3.5 times the clock phase settings)

FPGA Verilog HDL 读写SRAM(SRAM FPGA Verilog HDL to read and write)

说明：  “基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片，并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限，只能存储分辨率较小的图片(In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution)

数字钟，数字电子技术课程设计常用内容，基于basys3平台(Digital clock, digital electronic technology curriculum design commonly used, based on the basys3 platform)

说明：  用于FPGA的I2S接收模块，仅供学习和参考(audio-i2s receive.use fpga.)

使用CycloneIV芯片，实现对高精度ADCad9226的数据采集。内有详细代码说明，并附有调试结果(Use CycloneIV, to achieve high-precision data acquisition ADCad9226. Along with debugging results)