vga 显示测试

利用matlab，对偏振控制器进行仿真，最终在邦加球上进行显示(Using matlab, simulation of the polarization controller eventually be displayed on the Poincare Sphere)

altera remote updata cyclone5 平台例程，无nios核版本(altera remote updata cyclone5 platform routine do not use nios)

说明：  Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi

单口RAM带CLR信号的verilog程序。很详细的.(Single-port RAM with a CLR signal)

Implementation of Serial Infrared decoder for low-speed IrDA communications.

边界扫描技术相关资料，含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)

Altera官方FPGA电机控制的中文文档，很不错的参考资料(Altera Official FPGA Motor Control Chinese Document, Good Reference)

双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources. Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y)

verilog编写，巧妙的通过计数方式完成了三角波的波形，可直接对da输出。(verilog written, cleverly accomplished by counting the triangular waveform can be output directly to da.)

半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)