UART 完整

五级流水线CPU实现（带Hazard），还没来得及实现Cache求高人指教(pipeline CPU with Hazard)

可以产生8比特的采样波形，非常不错的VHDL程序(Sampling can produce 8-bit waveform, very good VHDL program)

VHDL之二進制轉BCD碼之程式碼，算完整的(Of binary to BCD code VHDL code, operator complete)

说明：  RLC Test程序,一个电子竞赛的题目。里面有详尽的源代码。(RLC Test procedures, an electronic race issue. There are detailed source code.)

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

基带数字信号通过成形滤波（选用升余弦滚降函数）然后进行载波调制(Base-band digital signal through the shaping filter (raised cosine roll-off optional function) and then proceed to carrier modulation)

主要是主机对寄存器进行配置传输数据

很好的fft学习程序感兴趣的同学可以看哈，下载一下。(it is very good )

32位全加器，另有一个采用流水线的版本，是基于verilog语言的，很实用，希望对大家有所帮助(32-bit full adder, while a pipelined version，code is based on verilog language, it is practical, we hope to help)

// 4 entry deep fast fifo module fifo4(clk, rst, clr,  din, we, dout, re, full, empty); parameter dw = 8; input clk, rst; input clr; input   [dw:1] din; input we; output  [dw:1] dout; input re; output full, empty; //////////////////////////////////////////////////////////////////// // // Local Wires // reg     [dw:1] mem[0:3]; reg     [1:0]   wp; reg     [1:0]   rp; wire    [1:0]   wp_p1; wire    [1:0]   wp_p2; wire    [1:0]   rp_p1; wire full, empty; reg gb; ///////////////////////////////////