E1（一级欧洲传输标准）

用Hspice实现一个三输入异或门，并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，7-8章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7- 8

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.

曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code

application of a galois field multiplication and normal multiplication

基于SOPC EP2C5开发板的I2C总线的A/D D/A例程-A/D AND D/A routings interfaced with i2c based on sopc ep2c5

用VHDL编写的EPP通信协议，可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes

Arbiter code for simulation purpose

关于MPEG压缩的程序，里面有较多的源代码和完整的说明是用MICROBLAZE完成的。(On the MPEG compression process, there are more source code and complete description is completed with MicroBlaze.)

说明：  FPGA PLL 分析，包括时序分析等等。。。。。。。。。(FPGA PLL Analysis)