E1（一级欧洲传输标准）

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates

这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。

VHDL在SOURCEINSIGHT的插件-VHDL in SOURCEINSIGHT plug-ins

VHDL设计的功能齐全的交通灯程序，经过仿真一切功能符合要求。-VHDL

利用分频可以产生一系列脉冲，根据输入脉冲的不同决定你得到的一系列脉冲频率-The use of sub-band can produce a series of pulses, according to input pulse of different decisions you have a series of pulse frequency

说明：  基于FPGA的USB接口设计，实现了USB与FPGA的通信(USB interface to FPGA-based design, implementation of the USB communication with the FPGA)

用流水线的方法实现16位乘法器，运算速度快，消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)

基于APB总线的UART详细设计方案和实现(APB-based detailed design and implementation of UART)

Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs