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说明: ADV7179芯片的驱动程序,基于FPGA硬件实现,已经验证可以使用(ADV7179 chip drivers, FPGA-based hardware implementation has been verified using)
- 2011-02-21 16:06:56下载
- 积分:1
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spi_src
在FPGA上实现CAN总线SPI接口通信,使用Verilog语言(Realize SPI interface communication of CAN bus on FPGA, using Verilog language)
- 2019-06-26 16:15:45下载
- 积分:1
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8051IP nuclear source code (VHDL). RAR
8051IP 核源代码(VHDL).RAR-8051IP nuclear source code (VHDL). RAR
- 2022-11-14 08:05:04下载
- 积分:1
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FPGA基于VHDL的Turbo码
如果本版权声明未从文件中删除,并且任何衍生作品包含原始版权声明和相关免责声明,则可以不受限制地使用和分发本源文件。
- 2022-03-06 11:21:33下载
- 积分:1
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Apply-of-turbo-code-in-LTE
turbo码在LTE中的实现,并在fpga中得到了实现(turbo code in LTE implementations, and have been achieved in fpga)
- 2021-01-14 20:28:46下载
- 积分:1
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tcp_ip_core_w_dhcp_latest.tar
以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
- 2018-08-23 14:35:01下载
- 积分:1
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pll
PLL 锁相环verilog程序 可以直接使用(The PLL can be used directly good use)
- 2014-08-28 19:06:33下载
- 积分:1
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yuandaima
以GPS为时间基准,实现多传感器器数据同步采集,整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)
- 2014-10-12 19:15:45下载
- 积分:1
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FSM
It is the FSM implemented in Xylinx 14.7 on FPGA
- 2015-09-28 15:50:09下载
- 积分:1
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1路视频光端机的发射端,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES...
1路视频光端机的发射端,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-08-08 19:22:01下载
- 积分:1