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一篇比较好的spi接口的vhdl实现的参考
一篇比较好的spi接口的vhdl实现的参考-A relatively good spi interface realize VHDL reference
- 2023-05-08 20:50:03下载
- 积分:1
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rectifier
三相PWM整流,实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ,can maintain the stable DC voltage)
- 2012-11-28 09:19:54下载
- 积分:1
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coe
自动计算fir滤波器系数的工具,不妨一试(Automatic calculation of filter coefficients fir tools, try)
- 2009-04-11 17:20:49下载
- 积分:1
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ANALYSIS-OF-FULL-ADDER
DESCRIPTION OF FULL ADDER
- 2013-11-12 13:32:19下载
- 积分:1
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truck_lights
Lights, Car light emulator for turn, stop and emergency
- 2012-11-06 18:27:06下载
- 积分:1
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LEDbrightness
使用PWM控制LED亮度的单片机C代码,共计十个亮度。(PWM control of LED brightness microcontroller C code, for a total of ten brightness.)
- 2012-06-08 21:14:10下载
- 积分:1
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LMS
least mean square algo implemented on verilog
- 2017-11-01 05:01:56下载
- 积分:1
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yiweijicunq
说明: 16位右移位寄存器
下面描述的是一个位宽为16位的右移位寄存器,实际具有环形移位的功能,是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时,输入信号的最低位移位到最高位,其余各位依次向右移动一位。(16-bit right shift register
The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)
- 2020-08-18 09:58:21下载
- 积分:1
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有关FIFO的代码
用VHDL语言写的代码 包括全局的输入时钟缓冲器来去抖动,块RAM模块65536*10,读数据,写数据,空标志信号的产生,满标志信号的产生,读写使能信号的产生七个模块!对各位有帮助噢!
- 2023-01-20 22:45:04下载
- 积分:1
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65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程...
65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程-65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole algorithm analysis including input a sum then multiply in the process
- 2022-01-30 18:45:51下载
- 积分:1