一个完整的

USB IPcoreIP核 包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)

Vhdl code for aarithmetic logic unit

基于FPGA的调制，实现了QPSK调制，所用芯片为Artera的CycloneIIEp2C5T114C8-FPGA-based modulation, realize the QPSK modulation, the chip used for Artera

Xilinx system generator

标准电视信号的同步生成程序，利用VHDL和原理图，利用Quartus综合-Standard television signal to generate the synchronization procedures, the use of VHDL and schematic diagram, using Quartus integrated

实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)

ov7620的CPLD采集程序，VHDL语言-ov7620 CPLD acquisition procedures, VHDL

网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。(a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong. tested.)

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

基于Verilog的八层电梯设计，能够实现自动化的电梯控制。-Verilog based on the eight-lift designed to automate the elevator control.