用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。...

用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)

说明：  verilog语言书写，单周期CPU源码(single period CPU)

数字钟vhdl主要分为正常显示与报时功能(Digital clock vhdl)

使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.

vhdl source code for 8 bit datapath logic

本人初学VHDL时编的比较系统的VHDL源程序 巨实用 (I am learning more systematic series of practical VHDL source Giant)

说明：  介绍如何使用 FPGA 内部的 ROM 以及程序对该 ROM 的数据读操作。(This paper introduces how to use the ROM inside the FPGA and how to read the data of the ROM by the program.)

UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )(UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB ))

说明：  在FPGA内，实现PS2键盘数据读取功能，verilog源代码(In the FPGA, achieving PS2 keyboard data read functions, verilog source code)

这是关于赢vhdl语言变得信号采集卡，很有实用性，大家可以来看看的。-This is about winning VHDL language has become signal acquisition card, is very practical, we can take a look at the.