FPGA将从CY7C68013读到的数写入SRAM

代码使用应用于 FPGA的VHDL代码，主要是告诉大家时序逻辑和组合逻辑的应用场合和区别，希望能够对大家有所帮助

11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated

ADI ad9361 vivado 下源代码(ADI ad9361 vivado source code)

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能(Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions)

高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog

说明：  LTE is an abbreviation for Long Term Evolution.

C源碼16C550 串口驅動，使用中斷收送RS232資料(16C550 UART Driver)

PWM整流器的死区延迟的VHDL编程，可以参考一下(VHDL programming PWM Rectifier dead-band delays)

基于VHDL实现加扰器解扰器的设计，与仿真。(VHDL-based scrambler descrambler design and simulation.)

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)