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100vhdlsimple
说明: 100个vhdl例子,对初学者很有用,可以用MAX+PLUS 2来编译仿真的(100 vhdl example, useful for beginners, you can use the MAX+ PLUS 2 to compile the simulation)
- 2010-05-02 10:01:58下载
- 积分:1
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at96
isa总线接口,可以实现与isa总线 的IO和MEMERY接口(isa bus interface can be achieved with the isa bus IO interfaces and MEMERY)
- 2008-05-15 20:36:51下载
- 积分:1
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ser_to_parr
很有用的10bit串并转换verilog程序,需要的可以拿去参考下,在quartusII上已验证过(Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII)
- 2012-05-21 16:21:22下载
- 积分:1
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一个用VerilogHDL语言编写的模6的二进制计数器
一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
- 2022-03-22 05:41:51下载
- 积分:1
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sep_fram_v0.0
直接序列扩频系统的收发系统,可以进行参数配置(this is a Verilog program )
- 2016-03-01 13:22:03下载
- 积分:1
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ADC TLC5510的测试程序,经过测试是非常简单和容易的
ADC TLC5510的测试程序,经过测试通过,十分简单好用-ADC TLC5510 test procedures, after the test is very simple and easy
- 2022-03-17 18:38:12下载
- 积分:1
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synplify-hand-book(English)
Syplify经典英文教程。内含众多实验例程,Lab 1 Basic Synplify Run;Lab 2 Analyzing Critical Path and Assigning Timing;Lab 3 FSM (Finite State Machine) Compiler Constraints and Attributes(Syplify classic English tutorial. Contains numerous experiments routine, you can help learners to quickly grasp Syplify tips, is a rare foreign experiments tutorial.)
- 2015-04-20 09:01:06下载
- 积分:1
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mp3decoder
verilog实现mp3解码程序,包括testbench(mp3 decoder verilog implementation procedures, including the testbench)
- 2020-12-31 15:38:59下载
- 积分:1
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awb
自动白平衡的verilog实现
通过逻辑实现了白平衡算法(awb design awb design awb design awb design awb design )
- 2012-09-04 13:09:50下载
- 积分:1
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sdio_slave
SDIO slave verilog code
- 2021-03-26 15:39:13下载
- 积分:1